Advanced Wireless Digital Baseband Signal Processing Beyond 100 Gbit/s

International audienceThe continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100 Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won't provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. In this paper, we highlight the challenges for wireless digital baseband signal processing beyond 100 Gbit/s and the limitations of today's architectures. Our focus lies on the channel decoding and MIMO detection, which are major sources of complexity in digital baseband signal processing. We discuss techniques on algorithmic and architectural level, which aim to close this gap. For the first time we show Turbo-Code decoding techniques towards 100 Gbit/s and a complete MIMO receiver beyond 100 Gbit/s in 28 nm technology

Identification d'un entrelaceur de type ARP d'un turbo-code inconnu.

International audienceIn this article, we give an efficient algorithm for recovering the ARP permutation of a given turbo encoder whenseveral noisy codewords are received. The algorithm presented here is based on a more general existing Turbo-code interleaveridentification algorithm [1]. However our algorithm is able to work with less intercepted codewords which opens the door forsecurity application [2].Dans cet article, nous proposons un algorithme efficace d'identification d'un entrelaceur ARP d'un turbo code à partir de quelques mots de code interceptés. Cet algorithme reprend les principes d'identification proposés dans [1] en les adaptant à la classe particulière des entrelaceurs ARP. L'intérêt principal est de nécessiter que quelques mots de code pour réaliser l'identification. Cela ouvre la porte à de nouvelles techniques de sécurité [2

Mitigating Blind Detection Through Protograph Based Interleaving for Turbo Codes

International audienceThe complexity involved to blindly detect the channel code parameters in the case of their imperfect knowledge is generally measured in terms of the minimum number of frames that an eavesdropper needs to observe for successful detection, adding an additional layer of privacy. In this work, starting from a defined almost regular interleaver for Turbo codes, we propose methods to construct a larger set of distinct interleavers that increases the minimum number of observations by a factor equal to the size of the constructed set. Furthermore, the generated sets of interleavers can be described by defining only a small number of parameters and are shown to achieve a comparable error correcting performance to base interleavers. To validate the proposed implementation-friendly method, an application example for information frame sizes K=128 bits and K=512 bits is provided for the construction of two sets of 8192 interleavers, prohibitively increasing detection complexity by state-of-the-art methods

Improved Non-Uniform Constellations for Non-Binary Codes Through Deep Reinforcement Learning

International audienceNon-binary forward error correction (FEC) codes have been getting more attention lately in the coding society thanks mainly to their improved error correcting capabilities. Indeed, they reveal their full potential in the case of a oneto-one mapping between the code symbols over Galois fields (GF) and constellation points of the same order. Previously, we proposed non-binary FEC code designs targeting a given classical constellation through the optimization of the minimum Euclidean distance between candidate codewords. To go a step further, a better Euclidean distance spectrum can be achieved through the joint optimization of code parameters and positions of constellation symbols. However, this joint optimization for high order GFs reveals to be intractable in number of cases to evaluate. Therefore in this work, we propose a solution based on the multi-agent Deep Q-Network (DQN) algorithm. Applied to non-binary turbo codes (NB-TCs) over GF(64), the proposal largely improves performance by significantly lowering the error floor region of the resulting coded modulation scheme

Construction of Symbol Transformations for Non-Binary Turbo Codes with Lowered Error Floor

International audienceNon-binary variants of Turbo and LDPC codes are known to provide significantly improved error correcting performance over their binary counterparts in particular for short frame sizes. One of the reasons is the possibility to directly map the code symbols to constellation symbols of higher order modulations. Moreover, being defined over higher-order Galois fields GF(q), Non-binary Turbo Codes offer high degrees of freedom in the code and interleaver design. In this work, first we analyse the interplay between component codes through the interleaver. Then, we propose a suitable design methodology for a GF(q) symbol transformation applied to the encoded frames by one of the component codes. By modifying the values of encoded symbols by one component code with respect to the other, the aim of such a transformation is to avoid reproducing error-prone sequences while taking into account the effect of the interleaver. Without added complexity to the encoding or to the decoding process, the transformations constructed through the proposed methodology significantly lower the error floor of non-binary turbo codes. Indeed, in a case study for two GF(16) codes, we show an improvement of up to 3 decades in the error floor

Iteration Overlap for Low-Latency Turbo Decoding

International audienceAchieving high decoding throughput and latency has been challenging for turbo decoders due to the limitations in terms of parallelism on component decoder level. To alleviate this issue, we propose an iteration overlap scheme able to apply a decoding schedule tailored to both, the decoder hardware architecture and the interleaver constraints. The proposal aims to minimize the achieved decoding latency without penalizing performance when compared to baseline decoders. To that end, we formulate the window schedule optimization problem when applying iteration overlap in pipelined Turbo Decoder hardware architectures. Then, we propose a method to find optimal window schedules under realistic assumptions. Results demonstrate that latency is reduced by 20 − 25% for most Long Term Evolution (LTE) interleaver configurations. For specific interleavers, the achieved latency reduction can be as high as 62%. This indicates that further latency savings could be achieved if iteration overlap is taken into account when designing interleavers

Simplified recursion units for Max-Log-MAP: New trade-offs through variants of Local-SOVA

International audienceThe Log-domain BCJR algorithm is broadly used in iterative decoding processes. However, the serial nature of the recursive state metric calculations is a limiting factor for throughput increase. A possible solution resorts to high-radix decoding, which involves decoding several successive symbols at once. Despite several studies aiming at reducing its complexity, high-radix processing remains the most computationally intensive part of the decoder when targeting very high throughput. In this work, we propose a reformulation specifically targeting the complexity reduction of the recursive calculation units by either limiting the required number of operations or by selectively removing unnecessary ones. We report a complexity reduction of the add-compare-select units in the order of 50% compared to the recently proposed local-SOVA algorithm. In addition, our results show that several performance/complexity trade-offs can be achieved thanks to the proposed simplified variants. This represents a promising step forward in order to implement efficient very high throughput convolutional decoders

Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm

International audienceNon-binary Turbo codes have been shown to outperform their binary counterparts in terms of error correcting performance yet the decoding complexity of the commonly used Min-Log-MAP algorithm prohibits efficient hardware implementations. In this work, we apply for the first time the recently proposed Local SOVA algorithm for decoding non-binary Turbo codes. Moreover, we propose a low complexity variant dedicated to the direct association with high order constellations denoted by the nearest neighbor Local SOVA. It considers only a limited amount of nearest competing constellation symbols for the soft output computation. Simulation results show that this approach allows a complexity reduction of up to 52% in terms of add-compare-select operations while maintaining the same error correcting performance compared to the Min-Log-MAP algorithm. It can even reach up to 80% if high code rates or frame error rates higher than 10^(−4) are targeted. The achieved complexity reduction represents a significant step forward towards hardware implementation

Fully Pipelined Iteration Unrolled Decoders -The Road to Tb/s Turbo Decoding

International audienceTurbo codes are a well-known code class used for example in the LTE mobile communications standard. They provide built-in rate flexibility and a low-complexity and fast encoding. However, the serial nature of their decoding algorithm makes high-throughput hardware implementations difficult. In this paper, we present recent findings on the implementation of ultra-high throughput Turbo decoders. We illustrate how functional parallelization at the iteration level can achieve a throughput of several hundred Gb/s in 28 nm technology. Our results show that, by spatially parallelizing the half-iteration stages of fully pipelined iteration unrolled decoders into X-windows of size 32, an area reduction of 40% can be achieved. We further evaluate the area savings through further reduction of the X-window size. Lastly, we show how the area complexity and the throughput of the fully pipelined iteration unrolled architecture scale to larger frame sizes. We consider the same target bit error rate performance for all frame sizes and highlight the direct correlation to area consumption